The present invention relates to a clock generation circuit using a PLL (Phase Locked Loop).
A PLL is a circuit which generates a clock that is phase-locked in an input signal, and has been used in various kinds of fields. FIG. 12 is a block diagram illustrating a general configuration of a PLL. In FIG. 12, a divider 1 divides an input clock CLKI in a preset division ratio 1/R, and outputs a reference clock CLKREF having a frequency that is 1/R of the input clock CLKI to a phase comparator 3 of a loop unit 2. The loop unit 2 is a circuit in which the phase comparator 3, a loop filter 4, a VCO (Voltage Controlled Oscillator) 5, and a divider 6 are connected in the form of a loop. Here, the phase comparator 3 compares phases of the reference clock CLKREF and a feedback clock CLKFB output from the divider 6, and outputs a phase error signal that indicates the phase error between the reference clock CLKREF and the feedback clock CLKFB. The loop filter 4 removes a high frequency component of the phase error signal, and outputs the phase error signal as a frequency control voltage. The VCO 5 oscillates with a frequency according to the frequency control voltage, and generates an output clock signal CLKO. The divider 6 divides the output clock CLKO in a preset division ratio 1/F, and outputs a feedback clock CLKFB having a frequency that is 1/F of the output clock CLKO to the phase comparator 3.
In this configuration, if the phase of the feedback clock CLKFB is delayed with respect to the phase of the reference clock CLKREF, the phase error signal that indicates the delay amount is output from the phase comparator 3. Accordingly, the frequency control voltage is increased to increase the frequency of the output clock CLKO, and feedback control is performed to make the phase of the feedback clock CLKFB relatively precede the phase of the reference clock CLKREF. On the other hand, in the case where the phase of the feedback clock CLKFB precedes the phase of the reference clock CLKREF, the phase error signal that indicates the amount of the advance is output from the phase comparator 3. Accordingly, the frequency control voltage is lowered to lower the frequency of the output clock CLKO, and feedback control is performed to make the phase of the feedback clock CLKFB be delayed relative to in respect to the phase of the reference clock CLKREF. As a result of performing the feedback control, the phase of the feedback clock CLKFB is synchronized with the phase of the reference clock CLKREF to be synchronized with the phase of the input clock CLKI, and an output clock CLKO having a frequency that is F/R times the input clock CLKI is obtained from the VCO 5.
As described above, the PLL is required to receive the supply of the input clock CLKI in order to generate the output clock CLKO. Here, in the case where a device that is a source of the input clock CLKI operates at all time, and the input clock CLKI is normally supplied to the PLL, it is possible for the PLL to generate the output clock CLKO for a device in which the PLL is installed using its input clock CLKI. However, according to systems, it may be difficult to constantly supply the input clock CLKI to the PLL through constant operation of a specified device. Accordingly, configuring a system may be considered in a manner such that a plurality of devices that are sources of the input clock CLKI (for example, device A and device B) is determined, and in the case where the device B stops its operation, for example, an input clock CLKI0 is supplied from the device A to the PLL, while in the case where the device A stops its operation, for example, an input clock CLKI1 is supplied from the device B to the PLL. According to this system, the supply of the input clock to the PLL is not intercepted, and for the device in which the PLL is installed, the PLL so continuously generates the output clock CLKO. However, the frequency of the input clock CLKI0 that is output by the device A may be different from the frequency of the input clock CLKI1 that is output by the device B. In this case, in order to generate the output clock CLKO having the same frequency to the PLL after switching the input clock, it is necessary to change the division ratio 1/R of the divider 1 or the division ratio 1/F of the divider 6 to suit the frequency of the input clock after the switching. However, even though the division ratio has been changed, the PLL moves out of synchronization when the switching of the input clock is performed, and thus the frequency of the output clock CLKO becomes unstable over a long term.
Here, with reference to FIG. 13, the above described problem will be described. FIG. 13 illustrates a counted value CNT1 of the input clock CLKI in the divider 1, the generation situation of the reference clock CLKREF, a counted value CNT6 of the output clock CLKO in the divider 6, and the generation situation of the feedback clock CLKFB. In this example, the divider 1 repeatedly performs down count for the input clock CLKI, and if the counted value becomes “0”, the divider 1 sets the counted value to R−1, and generates the reference clock CLKREF. Also, the divider 6 repeatedly performs down count for the output clock CLKO, and if the counted value becomes “0”, the divider 6 sets the counted value to F−1, and generates the feedback clock CLKFB. In a state where the feedback clock CLKFB is phase-synchronized with the reference clock CLKREF, the change of the counted value CNT1 of the divider 1 is in synchronization with the change of the counted value CNT6 of the divider 6.
The switching of the input clock CLKI is performed while the above described operation is performed, and if the frequency of the input clock after the switching becomes higher than that before the switching, as indicated by a broken line L1, the time gradient of the counted value CNT1 becomes steep, and thus the reference clock CLKREF is generated to be earlier than the generation timing of the feedback clock CLKFB. By contrast, if the frequency of the input clock after the switching becomes lower than that before the switching, as indicated by a broken line L2, the time gradient of the counted value CNT1 becomes shallow, and thus the reference clock CLKREF is generated to be delayed with respect to the generation timing of the feedback clock CLKFB. If the reference clock CLKREF having a large phase difference with respect to the feedback clock CLKFB is output to the phase comparator 3, a large phase error signal is generated, and thus the PLL moves out of synchronization.